UT Mixed-Signal Simulator
نویسندگان
چکیده
UT Mixed-Signal Simulator is a mixed-signal, mixeddomain, and mixed-language design environment which supports VHDL-AMS 1999, VHDL-2002, Verilog 2001, SystemVerilog 2005 assertions, and SystemC 2005.
منابع مشابه
A new public-domain program for mixed-signal simulation
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